/* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20161210-64(RM) * Copyright (c) 2000 - 2016 Intel Corporation * * Disassembling to non-symbolic legacy ASL operators * * Disassembly of SSDT-x11_3-ApCst.aml, Wed Jan 16 22:42:33 2019 * * Original Table Header: * Signature "SSDT" * Length 0x0000018A (394) * Revision 0x02 * Checksum 0x33 * OEM ID "PmRef" * OEM Table ID "ApCst" * OEM Revision 0x00003000 (12288) * Compiler ID "INTL" * Compiler Version 0x20160527 (538314023) */ DefinitionBlock ("", "SSDT", 2, "PmRef", "ApCst", 0x00003000) { External (_PR_.CPU0._CST, UnknownObj) // (from opcode) External (_PR_.CPU1, DeviceObj) // (from opcode) External (_PR_.CPU2, DeviceObj) // (from opcode) External (_PR_.CPU3, DeviceObj) // (from opcode) External (_PR_.CPU4, DeviceObj) // (from opcode) External (_PR_.CPU5, DeviceObj) // (from opcode) External (_PR_.CPU6, DeviceObj) // (from opcode) External (_PR_.CPU7, DeviceObj) // (from opcode) Scope (\_PR.CPU1) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU2) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU3) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU4) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU5) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU6) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } Scope (\_PR.CPU7) { Method (_CST, 0, NotSerialized) // _CST: C-States { Return (\_PR.CPU0._CST ()) } } }