/* * Intel ACPI Component Architecture * AML Disassembler version 20140210-00 [Feb 10 2014] * Copyright (c) 2000 - 2014 Intel Corporation * * Original Table Header: * Signature "SSDT" * Length 0x0000036A (874) * Revision 0x01 * Checksum 0x00 * OEM ID "APPLE " * OEM Table ID "CpuPm" * OEM Revision 0x00017000 (94208) * Compiler ID "INTL" * Compiler Version 0x20140210 (538182160) */ DefinitionBlock ("ssdt.aml", "SSDT", 1, "APPLE ", "CpuPm", 0x00017000) { External (\_PR_.CPU0, DeviceObj) External (\_PR_.CPU1, DeviceObj) External (\_PR_.CPU2, DeviceObj) External (\_PR_.CPU3, DeviceObj) External (\_PR_.CPU4, DeviceObj) External (\_PR_.CPU5, DeviceObj) External (\_PR_.CPU6, DeviceObj) External (\_PR_.CPU7, DeviceObj) Scope (\_PR_.CPU0) { Method (_INI, 0, NotSerialized) { Store ("ssdtPRGen version....: 17.0 / Mac OS X 10.13.2 (17C88)", Debug) Store ("target processor.....: i7-3770T", Debug) Store ("source processor.....: Intel(R) Core(TM) i7-3770T CPU @ 2.50GHz", Debug) Store ("baseFrequency........: 1600", Debug) Store ("frequency............: 2500", Debug) Store ("busFrequency.........: 100", Debug) Store ("logicalCPUs..........: 8", Debug) Store ("maximum TDP..........: 45", Debug) Store ("packageLength........: 22", Debug) Store ("turboStates..........: 12", Debug) Store ("maxTurboFrequency....: 3700", Debug) Store ("IvyWorkArounds.......: 3", Debug) Store ("machdep.xcpm.mode....: 0", Debug) } Name (APLF, 0x08) Name (APSN, 0x0D) Name (APSS, Package (0x1F) { /* Workaround for the Ivy Bridge PM 'bug' */ Package (0x06) { 0x0E75, 0x00AFC8, 0x0A, 0x0A, 0x2600, 0x2600 }, /* High Frequency Modes (turbo) */ Package (0x06) { 0x0E74, 0x00AFC8, 0x0A, 0x0A, 0x2500, 0x2500 }, Package (0x06) { 0x0E10, 0x00AFC8, 0x0A, 0x0A, 0x2400, 0x2400 }, Package (0x06) { 0x0DAC, 0x00AFC8, 0x0A, 0x0A, 0x2300, 0x2300 }, Package (0x06) { 0x0D48, 0x00AFC8, 0x0A, 0x0A, 0x2200, 0x2200 }, Package (0x06) { 0x0CE4, 0x00AFC8, 0x0A, 0x0A, 0x2100, 0x2100 }, Package (0x06) { 0x0C80, 0x00AFC8, 0x0A, 0x0A, 0x2000, 0x2000 }, Package (0x06) { 0x0C1C, 0x00AFC8, 0x0A, 0x0A, 0x1F00, 0x1F00 }, Package (0x06) { 0x0BB8, 0x00AFC8, 0x0A, 0x0A, 0x1E00, 0x1E00 }, Package (0x06) { 0x0B54, 0x00AFC8, 0x0A, 0x0A, 0x1D00, 0x1D00 }, Package (0x06) { 0x0AF0, 0x00AFC8, 0x0A, 0x0A, 0x1C00, 0x1C00 }, Package (0x06) { 0x0A8C, 0x00AFC8, 0x0A, 0x0A, 0x1B00, 0x1B00 }, Package (0x06) { 0x0A28, 0x00AFC8, 0x0A, 0x0A, 0x1A00, 0x1A00 }, /* High Frequency Modes (non-turbo) */ Package (0x06) { 0x09C4, 0x00AFC8, 0x0A, 0x0A, 0x1900, 0x1900 }, Package (0x06) { 0x0960, 0x00A6D6, 0x0A, 0x0A, 0x1800, 0x1800 }, Package (0x06) { 0x08FC, 0x009E10, 0x0A, 0x0A, 0x1700, 0x1700 }, Package (0x06) { 0x0898, 0x009575, 0x0A, 0x0A, 0x1600, 0x1600 }, Package (0x06) { 0x0834, 0x008D05, 0x0A, 0x0A, 0x1500, 0x1500 }, Package (0x06) { 0x07D0, 0x0084BF, 0x0A, 0x0A, 0x1400, 0x1400 }, Package (0x06) { 0x076C, 0x007CA3, 0x0A, 0x0A, 0x1300, 0x1300 }, Package (0x06) { 0x0708, 0x0074B1, 0x0A, 0x0A, 0x1200, 0x1200 }, Package (0x06) { 0x06A4, 0x006CE9, 0x0A, 0x0A, 0x1100, 0x1100 }, /* Low Frequency Mode */ Package (0x06) { 0x0640, 0x006549, 0x0A, 0x0A, 0x1000, 0x1000 }, Package (0x06) { 0x05DC, Zero, 0x0A, 0x0A, 0x0F00, 0x0F00 }, Package (0x06) { 0x0578, Zero, 0x0A, 0x0A, 0x0E00, 0x0E00 }, Package (0x06) { 0x0514, Zero, 0x0A, 0x0A, 0x0D00, 0x0D00 }, Package (0x06) { 0x04B0, Zero, 0x0A, 0x0A, 0x0C00, 0x0C00 }, Package (0x06) { 0x044C, Zero, 0x0A, 0x0A, 0x0B00, 0x0B00 }, Package (0x06) { 0x03E8, Zero, 0x0A, 0x0A, 0x0A00, 0x0A00 }, Package (0x06) { 0x0384, Zero, 0x0A, 0x0A, 0x0900, 0x0900 }, Package (0x06) { 0x0320, Zero, 0x0A, 0x0A, 0x0800, 0x0800 } }) Method (ACST, 0, NotSerialized) { Store ("Method _PR_.CPU0.ACST Called", Debug) Store ("CPU0 C-States : 13", Debug) /* Low Power Modes for CPU0 */ Return (Package (0x05) { One, 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, Zero, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x03, // Access Size ) }, 0x03, 0xCD, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000020, // Address 0x03, // Access Size ) }, 0x06, 0xF5, 0x015E } }) } Method (_DSM, 4, NotSerialized) { Store ("Method _PR_.CPU0._DSM Called", Debug) If (LEqual (Arg2, Zero)) { Return (Buffer (One) { 0x03 }) } Return (Package (0x02) { "plugin-type", One }) } } Scope (\_PR_.CPU1) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU1.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Store ("Method _PR_.CPU1.ACST Called", Debug) Store ("CPU1 C-States : 7", Debug) /* Low Power Modes for CPU1 */ Return (Package (0x05) { One, 0x03, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000000, // Address 0x01, // Access Size ) }, One, 0x03E8, 0x03E8 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000010, // Address 0x03, // Access Size ) }, 0x02, 0x94, 0x01F4 }, Package (0x04) { ResourceTemplate () { Register (FFixedHW, 0x01, // Bit Width 0x02, // Bit Offset 0x0000000000000020, // Address 0x03, // Access Size ) }, 0x03, 0xA9, 0x15E } }) } } Scope (\_PR_.CPU2) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU2.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } Scope (\_PR_.CPU3) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU3.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } Scope (\_PR_.CPU4) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU4.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } Scope (\_PR_.CPU5) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU5.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } Scope (\_PR_.CPU6) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU6.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } Scope (\_PR_.CPU7) { Method (APSS, 0, NotSerialized) { Store ("Method _PR_.CPU7.APSS Called", Debug) Return (\_PR_.CPU0.APSS) } Method (ACST, 0, NotSerialized) { Return (\_PR_.CPU1.ACST ()) } } }