| /* | = | /* |
| * Intel ACPI Component Architecture | * Intel ACPI Component Architecture | |
| * AML/ASL+ Disassembler version 20160422-64(RM) | * AML/ASL+ Disassembler version 20160422-64(RM) | |
| * Copyright (c) 2000 - 2016 Intel Corporation | * Copyright (c) 2000 - 2016 Intel Corporation | |
| * | * | |
| * Disassembling to non-symbolic legacy ASL operators | * Disassembling to non-symbolic legacy ASL operators | |
| * | * | |
| * Disassembly of iASLGR9ZOk.aml, Tue Jul 26 13:56:29 2022 | <> | * Disassembly of iASLurngMH.aml, Tue Jul 26 13:58:33 2022 |
| * | = | * |
| * Original Table Header: | * Original Table Header: | |
| * Signature "SSDT" | * Signature "SSDT" | |
| * Length 0x000008F0 (2288) | <> | * Length 0x00000972 (2418) |
| * Revision 0x01 | = | * Revision 0x01 |
| * Checksum 0xFE | <> | * Checksum 0xE3 |
| * OEM ID "APPLE " | = | * OEM ID "APPLE " |
| * OEM Table ID "CpuPm" | * OEM Table ID "CpuPm" | |
| * OEM Revision 0x00021500 (136448) | <> | * OEM Revision 0x00015600 (87552) |
| * Compiler ID "INTL" | = | * Compiler ID "INTL" |
| * Compiler Version 0x20140926 (538183974) | <> | * Compiler Version 0x20200925 (538970405) |
| */ | = | */ |
| DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00021500) | <> | DefinitionBlock ("", "SSDT", 1, "APPLE ", "CpuPm", 0x00015600) |
| { | = | { |
| External (_PR_.CPU0, DeviceObj) // Warning: Unknown object | <> | External (_PR_.CPU0, DeviceObj) // (from opcode) |
| External (_PR_.CPU1, DeviceObj) // Warning: Unknown object | External (_PR_.CPU1, DeviceObj) // (from opcode) | |
| External (_PR_.CPU2, DeviceObj) // Warning: Unknown object | External (_PR_.CPU2, DeviceObj) // (from opcode) | |
| External (_PR_.CPU3, DeviceObj) // Warning: Unknown object | External (_PR_.CPU3, DeviceObj) // (from opcode) | |
| External (_PR_.CPU4, DeviceObj) // Warning: Unknown object | External (_PR_.CPU4, DeviceObj) // (from opcode) | |
| External (_PR_.CPU5, DeviceObj) // Warning: Unknown object | External (_PR_.CPU5, DeviceObj) // (from opcode) | |
| External (_PR_.CPU6, DeviceObj) // Warning: Unknown object | External (_PR_.CPU6, DeviceObj) // (from opcode) | |
| External (_PR_.CPU7, DeviceObj) // Warning: Unknown object | External (_PR_.CPU7, DeviceObj) // (from opcode) | |
| = | ||
| Scope (\_PR.CPU0) | Scope (\_PR.CPU0) | |
| { | { | |
| Method (_INI, 0, NotSerialized) // _INI: Initialize | Method (_INI, 0, NotSerialized) // _INI: Initialize | |
| { | { | |
| Store ("ssdtPRGen version.....: 21.5 / Mac OS X 10.15.2 (19C57)", Debug) | <> | Store ("ssdtPRGen version....: 15.6 / Mac OS X 10.13.3 (17D102)", Debug) |
| Store ("custom mode...........: 0", Debug) | Store ("target processor.....: i7-3770K", Debug) | |
| Store ("host processor........: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz", Debug) | Store ("running processor....: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz", Debug) | |
| Store ("target processor......: i7-3770K", Debug) | ||
| Store ("number of processors..: 1", Debug) | ||
| Store ("baseFrequency.........: 1600", Debug) | Store ("baseFrequency........: 1600", Debug) | |
| Store ("frequency.............: 3500", Debug) | Store ("frequency............: 3500", Debug) | |
| Store ("busFrequency..........: 100", Debug) | Store ("busFrequency.........: 100", Debug) | |
| Store ("logicalCPUs...........: 8", Debug) | Store ("logicalCPUs..........: 8", Debug) | |
| Store ("maximum TDP...........: 77", Debug) | Store ("maximum TDP..........: 77", Debug) | |
| Store ("packageLength.........: 24", Debug) | Store ("packageLength........: 30", Debug) | |
| Store ("turboStates...........: 4", Debug) | Store ("turboStates..........: 10", Debug) | |
| Store ("maxTurboFrequency.....: 3900", Debug) | Store ("maxTurboFrequency....: 4500", Debug) | |
| Store ("CPU Workarounds.......: 3", Debug) | Store ("IvyWorkArounds.......: 3", Debug) | |
| Store ("machdep.xcpm.mode.....: 0", Debug) | Store ("machdep.xcpm.mode....: 1", Debug) | |
| } | = | } |
| Name (APLF, 0x09) | <> | Name (APLF, 0x08) |
| Name (APSN, 0x05) | Name (APSN, 0x0B) | |
| Name (APSS, Package (0x22) | Name (APSS, Package (0x27) | |
| { | = | { |
| Package (0x06) | Package (0x06) | |
| { | { | |
| <> | 0x1195, | |
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x2E00, | ||
| 0x2E00 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x1194, | ||
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x0F3D, | 0x2D00, | |
| 0x2D00 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x1130, | ||
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x2C00, | ||
| 0x2C00 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x10CC, | ||
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x2B00, | ||
| 0x2B00 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x1068, | ||
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x2A00, | ||
| 0x2A00 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x1004, | ||
| 0x00012CC8, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x2900, | ||
| 0x2900 | ||
| }, | ||
| Package (0x06) | ||
| { | ||
| 0x0FA0, | ||
| 0x00012CC8, | = | 0x00012CC8, |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2800, | 0x2800, | |
| 0x2800 | 0x2800 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0F3C, | 0x0F3C, | |
| 0x00012CC8, | 0x00012CC8, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2700, | 0x2700, | |
| 0x2700 | 0x2700 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0ED8, | 0x0ED8, | |
| 0x00012CC8, | 0x00012CC8, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2600, | 0x2600, | |
| 0x2600 | 0x2600 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0E74, | 0x0E74, | |
| 0x00012CC8, | 0x00012CC8, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2500, | 0x2500, | |
| 0x2500 | 0x2500 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0E10, | 0x0E10, | |
| 0x00012CC8, | 0x00012CC8, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2400, | 0x2400, | |
| 0x2400 | 0x2400 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0DAC, | 0x0DAC, | |
| 0x00012CC8, | 0x00012CC8, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2300, | 0x2300, | |
| 0x2300 | 0x2300 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0D48, | 0x0D48, | |
| 0x000120E0, | 0x000120E0, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2200, | 0x2200, | |
| 0x2200 | 0x2200 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0CE4, | 0x0CE4, | |
| 0x0001152F, | 0x0001152F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2100, | 0x2100, | |
| 0x2100 | 0x2100 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0C80, | 0x0C80, | |
| 0x000109B4, | 0x000109B4, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x2000, | 0x2000, | |
| 0x2000 | 0x2000 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0C1C, | 0x0C1C, | |
| 0xFE6F, | 0xFE6F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1F00, | 0x1F00, | |
| 0x1F00 | 0x1F00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0BB8, | 0x0BB8, | |
| 0xF35F, | 0xF35F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1E00, | 0x1E00, | |
| 0x1E00 | 0x1E00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0B54, | 0x0B54, | |
| 0xE884, | 0xE884, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1D00, | 0x1D00, | |
| 0x1D00 | 0x1D00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0AF0, | 0x0AF0, | |
| 0xDDDD, | 0xDDDD, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1C00, | 0x1C00, | |
| 0x1C00 | 0x1C00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0A8C, | 0x0A8C, | |
| 0xD36A, | 0xD36A, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1B00, | 0x1B00, | |
| 0x1B00 | 0x1B00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0A28, | 0x0A28, | |
| 0xC92B, | 0xC92B, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1A00, | 0x1A00, | |
| 0x1A00 | 0x1A00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x09C4, | 0x09C4, | |
| 0xBF1F, | 0xBF1F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1900, | 0x1900, | |
| 0x1900 | 0x1900 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0960, | 0x0960, | |
| 0xB546, | 0xB546, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1800, | 0x1800, | |
| 0x1800 | 0x1800 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x08FC, | 0x08FC, | |
| 0xAB9F, | 0xAB9F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1700, | 0x1700, | |
| 0x1700 | 0x1700 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0898, | 0x0898, | |
| 0xA229, | 0xA229, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1600, | 0x1600, | |
| 0x1600 | 0x1600 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0834, | 0x0834, | |
| 0x98E6, | 0x98E6, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1500, | 0x1500, | |
| 0x1500 | 0x1500 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x07D0, | 0x07D0, | |
| 0x8FD3, | 0x8FD3, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1400, | 0x1400, | |
| 0x1400 | 0x1400 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x076C, | 0x076C, | |
| 0x86F1, | 0x86F1, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1300, | 0x1300, | |
| 0x1300 | 0x1300 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0708, | 0x0708, | |
| 0x7E3F, | 0x7E3F, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1200, | 0x1200, | |
| 0x1200 | 0x1200 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x06A4, | 0x06A4, | |
| 0x75BD, | 0x75BD, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1100, | 0x1100, | |
| 0x1100 | 0x1100 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0640, | 0x0640, | |
| 0x6D6A, | 0x6D6A, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x1000, | 0x1000, | |
| 0x1000 | 0x1000 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x05DC, | 0x05DC, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0F00, | 0x0F00, | |
| 0x0F00 | 0x0F00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0578, | 0x0578, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0E00, | 0x0E00, | |
| 0x0E00 | 0x0E00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0514, | 0x0514, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0D00, | 0x0D00, | |
| 0x0D00 | 0x0D00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x04B0, | 0x04B0, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0C00, | 0x0C00, | |
| 0x0C00 | 0x0C00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x044C, | 0x044C, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0B00, | 0x0B00, | |
| 0x0B00 | 0x0B00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x03E8, | 0x03E8, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0A00, | 0x0A00, | |
| 0x0A00 | 0x0A00 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0384, | 0x0384, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0900, | 0x0900, | |
| 0x0900 | 0x0900 | |
| }, | }, | |
| Package (0x06) | Package (0x06) | |
| { | { | |
| 0x0320, | 0x0320, | |
| Zero, | Zero, | |
| 0x0A, | 0x0A, | |
| 0x0A, | 0x0A, | |
| 0x0800, | 0x0800, | |
| 0x0800 | 0x0800 | |
| }, | +- | |
| Package (0x06) | ||
| { | ||
| 0x02BC, | ||
| Zero, | ||
| 0x0A, | ||
| 0x0A, | ||
| 0x0700, | ||
| 0x0700 | ||
| } | = | } |
| }) | }) | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU0.ACST Called", Debug) | <> | Store ("Method CPU0.ACST Called", Debug) |
| Store ("CPU0 C-States : 13", Debug) | = | Store ("CPU0 C-States : 13", Debug) |
| Return (Package (0x05) | Return (Package (0x05) | |
| { | { | |
| One, | One, | |
| 0x03, | 0x03, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000000, // Address | 0x0000000000000000, // Address | |
| 0x01, // Access Size | 0x01, // Access Size | |
| ) | ) | |
| }, | }, | |
| One, | One, | |
| Zero, | Zero, | |
| 0x03E8 | 0x03E8 | |
| }, | }, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000010, // Address | 0x0000000000000010, // Address | |
| 0x03, // Access Size | 0x03, // Access Size | |
| ) | ) | |
| }, | }, | |
| 0x03, | 0x03, | |
| 0xCD, | 0xCD, | |
| 0x01F4 | 0x01F4 | |
| }, | }, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000020, // Address | 0x0000000000000020, // Address | |
| 0x03, // Access Size | 0x03, // Access Size | |
| ) | ) | |
| }, | }, | |
| 0x06, | 0x06, | |
| 0xF5, | 0xF5, | |
| 0x015E | 0x015E | |
| } | } | |
| }) | }) | |
| } | } | |
| Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method | Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method | |
| { | { | |
| Store ("Method _PR_.CPU0._DSM Called", Debug) | <> | Store ("Method CPU0._DSM Called", Debug) |
| If (LEqual (Arg2, Zero)) | = | If (LEqual (Arg2, Zero)) |
| { | { | |
| Return (Buffer (One) | Return (Buffer (One) | |
| { | { | |
| 0x03 | 0x03 | |
| }) | }) | |
| } | } | |
| Return (Package (0x02) | Return (Package (0x02) | |
| { | { | |
| "plugin-type", | "plugin-type", | |
| One | One | |
| }) | }) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU1) | Scope (\_PR.CPU1) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU1.APSS Called", Debug) | Store ("Method _PR_.CPU1.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU1.ACST Called", Debug) | <> | Store ("Method CPU1.ACST Called", Debug) |
| Store ("CPU1 C-States : 7", Debug) | = | Store ("CPU1 C-States : 7", Debug) |
| Return (Package (0x05) | Return (Package (0x05) | |
| { | { | |
| One, | One, | |
| 0x03, | 0x03, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000000, // Address | 0x0000000000000000, // Address | |
| 0x01, // Access Size | 0x01, // Access Size | |
| ) | ) | |
| }, | }, | |
| One, | One, | |
| 0x03E8, | 0x03E8, | |
| 0x03E8 | 0x03E8 | |
| }, | }, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000010, // Address | 0x0000000000000010, // Address | |
| 0x03, // Access Size | 0x03, // Access Size | |
| ) | ) | |
| }, | }, | |
| 0x02, | 0x02, | |
| 0x94, | 0x94, | |
| 0x01F4 | 0x01F4 | |
| }, | }, | |
| Package (0x04) | Package (0x04) | |
| { | { | |
| ResourceTemplate () | ResourceTemplate () | |
| { | { | |
| Register (FFixedHW, | Register (FFixedHW, | |
| 0x01, // Bit Width | 0x01, // Bit Width | |
| 0x02, // Bit Offset | 0x02, // Bit Offset | |
| 0x0000000000000020, // Address | 0x0000000000000020, // Address | |
| 0x03, // Access Size | 0x03, // Access Size | |
| ) | ) | |
| }, | }, | |
| 0x03, | 0x03, | |
| 0xA9, | 0xA9, | |
| 0x015E | 0x015E | |
| } | } | |
| }) | }) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU2) | Scope (\_PR.CPU2) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU2.APSS Called", Debug) | Store ("Method _PR_.CPU2.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU3) | Scope (\_PR.CPU3) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU3.APSS Called", Debug) | Store ("Method _PR_.CPU3.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU4) | Scope (\_PR.CPU4) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU4.APSS Called", Debug) | Store ("Method _PR_.CPU4.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU5) | Scope (\_PR.CPU5) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU5.APSS Called", Debug) | Store ("Method _PR_.CPU5.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU6) | Scope (\_PR.CPU6) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU6.APSS Called", Debug) | Store ("Method _PR_.CPU6.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| Scope (\_PR.CPU7) | Scope (\_PR.CPU7) | |
| { | { | |
| Method (APSS, 0, NotSerialized) | Method (APSS, 0, NotSerialized) | |
| { | { | |
| Store ("Method _PR_.CPU7.APSS Called", Debug) | Store ("Method _PR_.CPU7.APSS Called", Debug) | |
| Return (\_PR.CPU0.APSS) | Return (\_PR.CPU0.APSS) | |
| } | } | |
| Method (ACST, 0, NotSerialized) | Method (ACST, 0, NotSerialized) | |
| { | { | |
| Return (\_PR.CPU1.ACST ()) | Return (\_PR.CPU1.ACST ()) | |
| } | } | |
| } | } | |
| } | } | |